ADSP-214xx SHARC Processor Hardware Reference 3-45
External Port
The following steps are required when using self-refresh mode.
1. Set the
SDSRF bit to enter self-refresh mode
2. Poll the SDSRA bit in the SDRAM status register (SDSTAT) to deter-
mine if the SDRAM has already entered self-refresh mode.
3. Optionally: set the DSDCTL bit to freeze SDCLK
4. Optionally: clear the DSDCTL bit to re-enable SDCLK
5. SDRAM access occurs the SDRAM exits from self-refresh mode
The minimum time between a subsequent self-refresh entry and
exit command is the t
RAS
cycle. If a self-refresh request is issued
during any external port DMA, the SDC grants the request with
the t
RAS
cycle and continues DMA operation afterwards.
Forcing SDRAM Commands
The SDC does have some specific bits which can be used to aid in debug
and in specific system solutions.
Force Precharge All
Whenever an auto-refresh or a mode register set command is issued, the
internal banks are required to be in idle state. Setting bit 21 (=1) forces a
precharge all command to accomplish this. If the precharge all command
is not issued, the auto-refresh and mode register set commands can be ille-
gal depending on the current state.
Note that it is a good practice always to perform a force precharge all com-
mand before a forced refresh/mode register command.
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