ADSP-214xx SHARC Processor Hardware Reference 6-71
FFT/FIR/IIR Hardware Modules
Single Step Mode
Single step mode can be used for debug purposes. An additional debug
register is used in this mode.
1. Enable stop DMA during breakpoint hit in the emulator settings.
2. Clear the
IIR_HLD bit and enable IIR_DBGMODE and IIR_RUN bits in
IIRDEBUGCTL register.
3. Program FIR module according to the application.
4. In single step each iteration is updated in the emulator session.
Programming Example
In this example, an application needs IIR filtering for two channels of
data; channel 1 has six biquads and channel 2 has eight biquads. The win-
dow size for all channels is 32.
1. Create a circular buffer in internal memory for each channel’s data.
The buffer should be large enough to avoid overwriting data before
it is processed by the accelerator.
2. Configure internal memory buffers containing the 6 × 5 coeffi-
cients and the 6 × 2 Dk values for the channel 1 biquads, and the
8 × 5 coefficients and 8 × 2 Dk values of the channel 2 biquads.
3. Configure two TCBs in internal memory with each channel’s chain
pointer entry pointing to the next channel’s and the last channel’s
chain pointer entry pointing to the first in a circular fashion.
4. Program the IIRCTL2 register to use channel 1 TCB for 6 biquads
and a window size of 32, and channel 2 for 8 biquads and a win-
dow size of 32.
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