ADSP-214xx SHARC Processor Hardware Reference 4-15
Link Ports—ADSP-2146x
Buffer Status
The entire receive and transmit path form a 3-stage FIFO. Two
writes/reads can occur to the transmit/receive buffer by the core or DMA
before it signals a full/empty condition. Full/empty status for the link buf-
fer is shown by the
FFST bits in the LSTATx register. If the link port is
configured as a transmitter, then the FFST bits in the LSTATx register
reflect the status of the TXLBx register. If the link port is configured as a
receiver, then the FFST bits in LSTATx register reflect the status of RXLBx.
Core Transfers
In applications where the latency of link port DMA transfers to and from
internal memory is too long, or where a process is continuous and has no
block boundaries, the processor core may read or write link buffers
directly using the full or empty status bit of the link buffer to automati-
cally pace the operation. The full or empty status of a particular link
buffer can be determined by reading the LSTATx bits in the LCTL register.
DMA should be disabled if reading or writing to the link port
buffers.
If a read is attempted from an empty receive buffer, the core stalls (hangs)
until the link port completes reception of a word. If a write is attempted
to a full transmit buffer, the core stalls until the external device accepts the
complete word. Up to four words (2 in the receiver and 2 in the transmit-
ter) may be sent without a stall before the receiver core or DMA must read
a link buffer register.
To support debugging buffer transfers, the processor has a buffer hang dis-
able (
LP_BHD) bit. When set (=1), this bit prevents the processor core from
detecting a buffer-related stall condition, permitting debugging of this
type of stall condition.
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