Data Transfer
8-10 ADSP-214xx SHARC Processor Hardware Reference
• The number of free quadlets in the local channel buffer falls below
the threshold for receive channels or:
free quadlets <=
MLB_LCBCRx (programmed using TH bits)
• A receive channel detects a broken packet (ReceiverBreak,
AsyncBreak, ControlBreak or ReceiverProtocolError).
Configuring local channel buffer memory is accomplished using the
MLB_LCBCRx register. For more information, see “Programming Model” on
page 8-16.
DMA
There are two modes of DMA—Ping-pong buffering and circular
buffering.
There are 31 DMA channels for the 31 logical channels. Each channel can
address up to 16k words.
The DMA address is comprised of:
• A 5-bit base configured in the MLB base register set (MLB_SBCR,
MLB_IBCR, MLB_ABCR or MLB_CBCR for the corresponding channel
data type). The 5-bit base is the same for all the channels of the
same type (for example for all synchronous RX channels
MLB_SBCR31–16 act as the base).
• A 14-bit offset configured using the BCA bits in the MLB_CCBCRx reg-
ister. The register holds the lower 14 bits (bits 31–18 for start
address and 15–2 for end address). Bits 17–16 and bits 1–0 are
reserved and must always be written with zero.
For example, if the internal address is 0xC0100, then 19 bits of the
address translates to address 0x40100 because the internal memory offset
for the ADSP-214xx is 0x0008 0000.
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