Programming Models
22-14 ADSP-214xx SHARC Processor Hardware Reference
Post Divider
Use the following procedure and the example shown in Listing 22-2 to
program or reconfigure the divider.
1. Disable any peripheral (configured with PCLK=CCLK/2). Note that
the peripherals cannot be enabled when changing VCO to core
clock ratio.
2. Select the PLLD divider by setting the PLLD bits (6–7) in the
PMCTL register and enable the DIVEN bit.
3. Wait 15 CCLK cycles. During this time, the new divisor ratios are
picked up on the fly and the clocks smoothly transition to their
new values after a maximum of 14 core clock CCLK cycles.
4. Re-enable the peripherals.
Listing 22-2. Post Divider
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP; /* bypass disabled*/
bit set ustat2 DIVEN|PLLD4; /* set and enable post divisor */
dm(PMCTL) = ustat2;
lcntr = 15, do wait until lce;
wait: nop;
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