FIR Accelerator
6-46 ADSP-214xx SHARC Processor Hardware Reference
Bit 11 of the
DBGADDR register selects coefficient memory if set (=1) and
selects delay line memory in cleared (=0).
In the debug mode, the read data register (DBGMEMRDDAT) returns the con-
tents of the memory location pointed to by the address register. Data can
be written into any memory location using DBGMEMWRDAT register writes. If
the address auto increment bit (FIR_ADRINC) is set, the address register
auto increments on DBGMEMWRDAT writes and DBGMEMRDDAT reads. During
auto increment, the FIR_DBGADDR register cannot cross the data memory/
coefficient memory boundary.
Single Step Mode
Programs can single step through the MAC operations and observe the
memory contents after each step. The FIR_DBGMODE/FIR_HLD and FIR_RUN
bits control the FIR MAC units.
Emulation Considerations
In FIR debug mode, the DMA operations are not observable.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
FIR Accelerator Effect Latency
After the FIR registers are configured the effect latency is 1.5 PCLK cycles
minimum and 2 PCLK cycles maximum. Writes to the PMCTL1 register have
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