Operating Modes
11-10 ADSP-214xx SHARC Processor Hardware Reference
Figure 11-3 on page 11-11 through Figure 11-5 on page 11-13 show dif-
ferent packing modes including valid data hold inputs.
As shown in the figures,
PDAP_DATA and PDAP_HOLD are driven by the inac-
tive edges of the clock (falling edge in the above figures) and these signals
are sampled by the active edge of the clock (rising edge in the figures).
PDAP Data Masking
For input data widths less than 20, inputs are aligned to the MSB pins.
Additionally all PDAP inputs can be masked (IDP_PDAP_CTL register) to
form user specific data streams from any input pins. Clearing the MASK bits
(=0) disables data from the corresponding DAI or external port pin.
PDAP Data Packing
Multiple latched parallel sub word samples may be packed into 32-bit
words for efficiency. The frame sync input is used to hold off latching of
the next sample (that is, ignore the clock edges). The data then flows
through the FIFO and is transferred by a dedicated DMA channel into the
core’s memory as with any IDP channel. As shown in Figure 11-2, the
PDAP can accept input words up to 20 bits wide, or can accept input
words that are packed as densely as four input words up to eight bits wide.
The
IDP_PDAP_PACKING bits define the packing format. Based on the
PDAP packing the data buffer format changes as shown in Figure 11-9.
No Packing
No packing provides for 20 bits coming into the packing unit and 32 bits
going out to the FIFO in a single cycle. On every clock edge, 20 bits of
data are moved and placed in a 32-bit register, left-aligned. That is, bit 19
maps to bit 31. The lower bits, 11–0, are always set to zero.
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