ADSP-214xx SHARC Processor Hardware Reference 3-17
External Port
In contrast, when no predictive read (
PREDIS bit = 1) is used, the delay
between two reads increases. Note that both DMA and the processor core
have predictive read capability. Further note that the PREDIS bit should
not be changed when the AMI is performing an access. Predictive reads
reduce peripheral performance.
If an access to an external FIFO is required at maximum speed, programs
can also clear PREDIS (=0). The last access before a non AMI access should
be a dummy AMI write access. This ensures that the last predictive read is
omitted.
The PREDIS bit (bit 21) is a global bit that when set in any of the
AMICTLx registers provides access to all memory banks.
SDRAM Controller
(ADSP-2147x/ADSP-2148x)
The SHARC processors support a glueless interface with any of the stan-
dard SDRAMs. The following sections provide detail about this interface.
Features
The SDRAM controller (SDC) can support up to 254M words of
SDRAM in four banks. Bank 0 can accommodate up to 62M words, and
banks 1, 2, and 3 can accommodate up to 64M words each. The interface
has the following additional features.
• I/O width 16-bits, I/O supply 3.3 V
• Types of 32, 64, 128, 256, and 512M bit with I/O of x4, x8, and
x16
• Page sizes of 128, 256, 512, 1k, 2k words
• Variable memory address map (bank or page interleaving)
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