ADSP-214xx SHARC Processor Hardware Reference 2-17
I/O Processor
IIR Accelerator TCB
The IIR accelerator supports circular buffer chained DMA. Table 2-19
shows the required TCBs for chained DMA.
In the IIR accelerator DMA, two different TCB loading sequences
are available: one TCB loads five parameters for the coefficients
(IIRCTL2, CIIIR, CMIIR, CCIIR and CPIIR). The second loads 10
parameters for the data (IIRCTL2, IIIR, IMIIR, ICIIR, IBIIR, OIIIR,
OMIIR, OCIIR, OBIIR and CPIIR).
Table 2-19. IIR TCBs
Address Register
CP[18:0] CPIIR
CP[18:0] + 0x1 CCIIR
CP[18:0] + 0x2 CMIIR
CP[18:0] + 0x3 CIIIR
CP[18:0] + 0x4 OBIIR
CP[18:0] + 0x5 OCIIR
CP[18:0] + 0x6 OMIIR
CP[18:0] + 0x7 OIIIR
CP[18:0] + 0x8 IBIIR
CP[18:0] + 0x9 ICIIR
CP[18:0] + 0xA IMIIR
CP[18:0] + 0xB IIIIR
CP[18:0] + 0xC IIRCTL2
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