ADSP-214xx SHARC Processor Hardware Reference 2-25
I/O Processor
The direction (receive or transmit) of the peripheral determines the direc-
tion of data transfer. When the port receives data, the I/O processor
automatically transfers the data to internal memory. When the port needs
to transmit a word, the I/O processor automatically fetches the data from
internal memory. Figure 2-1 on page 2-26 shows more detail on DMA
channel data paths.
Peripheral to External Memory (SPORTs)
The SPORTs allow direct DMA transfers between the SPORT and exter-
nal memory space. Programs do not need to first copy data into internal
memory and then run an external port DMA to external memory space.
Internal Memory to Internal Memory
The SHARC processors can use memory-to-memory DMA to transfer
64-bit blocks of data between internal memory locations.
DMA Controller Addressing
Figure 2-1 shows a block diagram of the I/O processor’s address generator
(DMA controller). “Standard DMA Parameter Registers” on page 2-4 lists
the parameter registers for each DMA channel. The parameter registers are
uninitialized following a processor reset.
The I/O processor generates addresses for DMA channels much the same
way that the Data Address Generators (DAGs) generate addresses for data
memory accesses. Each channel has a set of parameter registers, including
an index register and modify register that the I/O processor uses to address
a data buffer in internal memory. The index register must be initialized
with a starting address for the data buffer. As part of the DMA operation,
the I/O processor outputs the address in the index register onto the pro-
cessor’s I/O address bus and applies the address to internal memory
during each DMA cycle—a clock cycle in which a DMA transfer is taking
place.
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