ADSP-214xx SHARC Processor Hardware Reference 15-33
Serial Peripheral Interface Ports
DMA Slave Transfers
To configure the SPI port for slave mode DMA transfers:
1. Define DMA receive (or transmit) transfer parameters by writing
to the
IISPIx, IMSPIx, and CSPIx registers.
2. Write to the SPIDMACx register to enable the SPI DMA engine
(SPIDEN, bit 0). And configure the following:
• A receive access (SPIRCV = 1) or
• A transmit access (SPIRCV = 0)
Chained DMA Transfers
The sequence for setting up and starting a chained DMA is outlined in the
following steps.
1. Clear the chain pointer register.
2. Configure the TCB associated with each DMA in the chain except
for the first DMA in the chain.
3. Write the first three parameters for the initial DMA to the IISPI,
IMSPI, CSPI, IISPIB, IMSPIB, and CSPIB registers directly.
4. Configure the DMA settings for the entire sequence, enabling
DMA and DMA chaining in the
SPIDMAC register.
5. Begin the DMA by writing the address of a TCB (describing the
second DMA in the chain) to the
CPSPI, CPSPI registers.
Stopping SPI Transfers
External transfer completion is indicated by the SPI status bit SPIFE. For
core-driven transfers it shows that the read transfer (TIMOD = 00) or write
transfer (
TIMOD = 01) has been completed on the external interface. For
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