ADSP-214xx SHARC Processor Hardware Reference 3-69
External Port
(hardware reset) immediately after reset, timing parameter cannot be met,
causing data loss. The DDR2 device must be re-initialized and the DDR2
DLL must be re locked to use the DDR2 again.
Running reset (RESETOUT pin as an input) does not reset the DDR2
controller.
Disabling the Controller
If the DDR2 interface is not used, the following bits should be config-
ured. This is required get maximum power reduction.
•In the DDR2CTL0 register, set (=1) the following bits: DIS_DDR2CTL,
DIS_DDR2CLK1 and DIS_DDR2CKE to disable the controller and its
I/O pads.
•In the DDR2PADCTL0 register (bits 9, 19 and 29) and DDR2PADCTL1
register (bits 9 and 19), set (=1) all the PWD bits to power-down the
pad receivers.
Initialization Sequence
After the DDR2PSS bit is set in the DDR2CTL0 register, the DDR2 controller
starts the power-up initialization sequence which occurs in the following
order. Note that this procedure is performed by the DDR2 controller and
user intervention is not required.
1. Brings
DDR2CKE high, drive a NOP command.
2. Wait a minimum of 400 ns (with
NOP or DESELECT commands).
3. Issue a precharge all command. Wait t
RPA
period.
4. Issue a load EMR(2) command. Wait t
MRD
period.
5. Issue a load EMR(3) command. Wait t
MRD
period.
6. Issue a load EMR command. Wait t
MRD
period.
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