ADSP-214xx SHARC Processor Hardware Reference 15-31
Serial Peripheral Interface Ports
Core Master Transfers
When a device is to be used as a master, configure the ports using the fol-
lowing procedure.
1. Initiate the SPI transfer by writing or reading to/from SPI buffers.
The trigger mechanism for starting the transfer is dependant upon
the
TIMOD bits in the SPICTLx registers. See Table 15-6 on
page 15-13 for more details.
2. The SPI generates the programmed clock pulses on SPICLK. The
data is shifted out of MOSI and shifted in from MISO simultaneously.
Before starting to shift, the transmit shift register is loaded with the
contents of the TXSPIx registers. At the end of the transfer, the con-
tents of the receive shift register are loaded into the RXSPI buffer.
3. With each new buffer access, the SPI continues to send and receive
words, according to the SPI transfer mode (TIMOD bit in SPICTLx
registers). See Table 15-6 on page 15-13 for more details.
4. If there are no further SPI buffer accesses the SPICLK signal is
stalled until new core requests are received.
DMA Master Transfers
To configure the SPI port for master mode DMA transfers:
1. Define DMA receive (or transmit) transfer parameters by writing
to the IISPIx, IMSPIx, and CSPIx registers.
2. Write to the SPIDMACx register to enable the SPI DMA engine
(
SPIDEN, bit 0). And configure the following:
• A receive access (SPIRCV = 1) or
• A transmit access (
SPIRCV = 0)
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