DMA Channel Registers
2-4 ADSP-214xx SHARC Processor Hardware Reference
Standard DMA Parameter Registers
The parameter registers described below control the source and destina-
tion of the data, the size of the data buffer, and the step size used.
The length of DMA registers for the serial ports have changed from
earlier SHARC processors in order to accommodate data transfers
to/from external memory.
Index registers. These registers, shown in Table 2-2, provide an internal
memory address that acts as a pointer to the next internal memory DMA
read or write location. All internal index addresses are based on an internal
memory offset of 0x80000.
Table 2-2. Index Registers
Register Name Width (Bits) Description
IISP0–7A 28 SPORTxA (supports external addresses)
IISP0–7B 28 SPORTxB (supports external addresses)
IISPI 19 SPI
IISPIB 19 SPIB
IDP_DMA_I0–7 19 IDPx
IDP_DMA_I0–7A 19 IDPx index A (ping pong)
IDP_DMA_I0–7B 19 IDPx index B (ping pong)
IIUART0RX 19 UART0 Receiver
IIUART0TX 19 UART0 Transmitter
IILB0–1 19 Link Port0–1
IIFIR 19 Accelerator FIR data input
CIFIR 19 Accelerator FIR coeff input
OIFIR 19 Accelerator FIR output
IIIIR 19 Accelerator IIR data input
CIIIR 19 Accelerator IIR coeff input
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