ADSP-214xx SHARC Processor Hardware Reference 9-35
Digital Application/Digital Peripheral Interfaces
DAI Miscellaneous Interrupts
As described above, the DAI interrupt controller registers provide 10 inde-
pendently-configurable interrupts labeled as DAI_31-22_INT. Any trigger
on the routed DAI inputs DAI_INT_31-22_I can cause an interrupt latch
event in DAI_IMASK register if unmasked.
There are two signal naming conventions: the DAI interrupt con-
troller bits are named DAI_31-22_INT and its corresponding SRU
signals are named DAI_INT_31-22_I.
Signals from the SRU can be used to generate interrupts. For example,
when DAI_30_INT (bit 30) of DAI_IMASK_H is set to one, any signals from
the external miscellaneous channel A2 generate an interrupt. If set to one,
DAI interrupts trigger an interrupt in the core and the interrupt latch is
set. A read of this bit does not reset it to zero. The bit is only set to zero
when the cause of the interrupt is cleared. A DAI interrupt indicates the
source (in this case, external miscellaneous A, channel 2), and checks the
IVT for an instruction (next operation) to perform.
Table 9-6 provides an overview of DAI miscellaneous interrupts.
DPI Miscellaneous Interrupts
As described above, the DPI interrupt controller registers provide 9 inde-
pendently-configurable interrupts labeled as DPI_13-5_INT. Any trigger on
the routed DPI inputs
MISCB8-0_I can cause an interrupt latch event in
DPI_13-5_INT if enabled.
Table 9-6. DAI Miscellaneous Interrupt Overview
Interrupt
Source
Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
DAI MISCA
(10 channels)
– Rising edge
– Falling edge
– Rising/falling edge
Read-to-clear
DAI_IRPTL_x
+ RTI instruction
P0I, P12I
To Next Page
Loading...
Need help?
General
