ADSP-214xx SHARC Processor Hardware Reference 6-67
FFT/FIR/IIR Hardware Modules
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
IIR Accelerator Effect Latency
After the IIR registers are configured the effect latency is 1.5
PCLK cycles
minimum and 2 PCLK cycles maximum. Writes to the PMCTL1 register have
an effect latency of two PCLK cycles. Wait for at least four CCLK cycles after
selecting another accelerator before accessing any of its registers.
IIR Throughput
Data throughput is one 32-bit data word per peripheral clock cycle for
writes to memory, provided there are no conflicts. Read throughput from
memory, throughput is one 32-bit data word per two peripheral clock
cycles.
IIR throughput is calculated as follows:
Total number of peripheral clock cycles = (TCB load + 5 × B × W) × C
where:
• B = number of bi-quads
• W = Window size
• C = number of channels
• TCB load = 36
PCLK cycles
•5 × B – Number of cycles to calculate B biquads (Note: This does
not include the coefficient loading cycles as coefficients need to be
loaded only once.)
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