ADSP-214xx SHARC Processor Hardware Reference 10-53
Serial Ports
• When the frame sync pulse >
SCLK period.
• In late frame sync mode if the frame sync pulse is not active during
the whole transmission/reception a frame sync error is generated.
Error Status
Each SPORT can generate an interrupt if a DERR_A, DERR_B, or FSYNC_ERR
error occurs. The
SPERRCTLx registers control and report the status of the
interrupts generated by each SPORT.
SPORT sticky error bits can be cleared in two ways:
1. By disabling the SPORT (frame sync error) or disabling the corre-
sponding channel by itself (for
DERR_A, DERR_B).
2. By writing a 1 to the interrupt status bits in the SPERRCTLx register.
When sticky bits are cleared, interrupts are also cleared.
Only one error interrupt is connected for all serial ports together. So when
an error occurs the programs should read the sticky status bits and detect
which interrupt caused the error.
An additional register is provided to read all sport interrupt status bits
together. The SPERRSTAT register shows the status of all SPORT error
interrupts. This register also shows the latched interrupt status, but only
when the interrupt is enabled for that error.
Debug Features
The following sections provide information on debugging features avail-
able with the serial ports.
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