Interrupts
15-26 ADSP-214xx SHARC Processor Hardware Reference
(bit 12) in the
IMASK register. To service the secondary SPI port, unmask
(set = 1) the SPILIMSK bit (bit 19) in the LIRPTL register. For a list of these
bits, see the SHARC Processor Programming Reference.
When using DMA transfers, programs must also specify whether to gener-
ate interrupts based on transfer or error status. For DMA transfer status
based interrupts, set the INTEN bit in the SPIDMAC register. Depending
upon the state of INTETC bit the interrupt can be generated when the inter-
nal count becomes zero or the external transfer is complete. Otherwise, set
the INTERR bit to trigger the interrupt if one of the error conditions occurs
during the transmission—for example a multimaster error (MME), transmit
buffer underflow (TUNF – only if SPIRCV = 0), or receive buffer overflow
(ROVF – only if SPIRCV = 1).
During core-driven transfers, the TUNF and ROVF error conditions
do not generate interrupts.
When DMA is disabled, the processor core may read from the RXSPI regis-
ter or write to the TXSPI data buffer. The RXSPI and TXSPI buffers are
memory-mapped IOP registers. A maskable interrupt is generated when
the receive buffer is not empty or the transmit buffer is not full. The TUNF
and ROVF error conditions do not generate interrupts in these modes.
Multi Master Error
The SPIMME bit (1) is set when the SPI_DS_I input pin of a device that is
enabled as a master is driven low by some other device in the system. This
occurs in multimaster systems when another device is also trying to be the
master.
To enable this feature, set the ISSEN bit in the SPICTL register. As soon as
this error is detected, the following actions are taken:
1. The SPIMS control bit in SPICTL is cleared, configuring the SPI
interface as a slave.
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