ADSP-214xx SHARC Processor Hardware Reference 9-33
Digital Application/Digital Peripheral Interfaces
broad categories, programs can indicate which interrupts are high and
which are classified as low.
Functional Description
There are several registers in the DAI interrupt controller that can be con-
figured to control how the DAI interrupts are reported to and serviced by
the core’s interrupt controller.
The DAI contains its own interrupt controller that indicates to the core
when DAI audio peripheral related events have occurred. Since audio
events generally occur infrequently relative to the SHARC processor core,
the DAI interrupt controller reduces all of its interrupts onto two inter-
rupt signals within the core’s primary interrupt systems.
Among other options, each DAI interrupt can be mapped either as a high
or low priority interrupt in the primary interrupt controller. Certain DAI
interrupts can be triggered on either the rising or the falling edge of the
signals, and each DAI interrupt can also be independently masked.
DAI Interrupt Channels
The DAI can handle up to 32 interrupts as shown below.
• 8 x IDP DMA channels (Input data port)
• 2 x IDP FIFO status (Input data port)
• 10 x miscellaneous interrupts
• 8 x S/PDIF receiver status
• 4 x SRC (sample rate converter)
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