Interrupts
10-50 ADSP-214xx SHARC Processor Hardware Reference
Internal Transfer Completion
Each serial port has an interrupt associated with it. For each SPORT, both
the A and B channel transmit and receive data buffers share the same
interrupt vector. The interrupts can be used to indicate the completion of
the transfer of a block of serial data when the serial ports are configured
for DMA. They can also be used to perform single word transfers (refer to
“Single Word Transfers” on page 10-43). The priority of the serial port
interrupts is shown in Table 2-28 on page 2-36.
Multiple interrupts can occur if both SPORTs transmit or receive data in
the same cycle. Any interrupt can be masked in the IMASK register; if the
interrupt is later enabled in the LIRPTL register, the corresponding inter-
rupt latch bit in the IRPTL or LIRPTL registers must be cleared in case the
interrupt has occurred in the same time period.
SPORT interrupts occur on the second peripheral clock (PCLK)
after the last bit of the serial word is latched in or driven out.
When serial port data packing is enabled (PACK = 1 in the SPCTLx regis-
ters), the transmit and receive interrupts are generated for 32-bit packed
words, not for each 16-bit word.
Each DMA channel has a count register (CSPxA/CSPxB), which must be
initialized with a word count that specifies the number of words to trans-
fer. The count register decrements after each DMA transfer on the
channel. When the word count reaches zero, the SPORT generates an
interrupt, then automatically stops the DMA channel.
Shared Channels
Both the A and B channels share a common interrupt vector in the inter-
rupt-driven data transfer mode, regardless of whether they are configured
as a transmitter or receiver.
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