ADSP-214xx SHARC Processor Hardware Reference 11-15
Input Data Port
Core Transfers
The core transfers require that the serial peripheral at the SIP writes data
to the IDP_DATAx_I pin (DATA or DAI pins for PDAP) according to the
selected input format used. These data are automatically moved to the
IDP_FIFO register without DMA intervention.
The output of the FIFO can be directly fetched by reading from the
IDP_FIFO buffer. The IDP_FIFO buffer is used only to read and remove the
top sample from the FIFO, which is a maximum of eight locations deep.
When this register is read, the corresponding element is removed from the
IDP FIFO, and the next element is moved into the
IDP_FIFO register. A
mechanism is provided to generate an interrupt when more than a speci-
fied number of words are in the FIFO. This interrupt signals the core to
read the
IDP_FIFO register.
The number of data samples in the FIFO at any time is reflected in the
IDP_FIFOSZ bit field (bits 31-28 in the DAI_STAT0 register), which tracks
the number of samples in FIFO.
Table 11-8. IDP_FIFO Register Bit Descriptions
Bit Name Description
2–0 CHAN_ENC IDP Channel Encoding. These bits indicate the serial input port
channel number that provided this serial input data.
Note: This information is not valid when data comes from the PDAP.
3LR_STATLeft/Right Channel Status. Indicates whether the data in bits 31-4 is
the left or the right audio channel as dictated by the frame sync sig-
nal. The polarity of the encoding depends on the serial mode selected
in IDP_SMODE for that channel. See Table A-90 on page A-176.
31–4 SDATA Input Data (Serial). Some LSBs can be zero, depending on the
mode.
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