ADSP-214xx SHARC Processor Hardware Reference 22-3
Power Management
multiplication range, the processor uses a combination of programmable
multipliers in the PLL feedback circuit and output configuration blocks.
The processor uses an on-chip, phase-locked loop (PLL) to generate its
internal clock, which is a multiple of the
CLKIN frequency. The PLL
requires some time to achieve phase lock and CLKIN must be valid for a
minimum time period during reset before the RESET signal can be deas-
serted. For information on minimum clock setup, external crystal use, and
range for any given CLKIN frequency, see the appropriate product data
sheet.
A detailed diagram along with specific equations on the derivation
of VCO frequency with reference to CLKIN can be found in the
appropriate product data sheet.
PLL Input Clock
If an external clock oscillator is used, it should NOT drive the CLKIN pin
when the processor is not powered. The clock must be driven immediately
after power-up; otherwise, internal gates stay in an undefined (hot) state
and can draw excess current. After power-up, allow sufficient time for the
oscillator to start up, reach full amplitude, and deliver a stable CLKIN signal
to the processor before the reset is released. This may take several millisec-
onds and depends on the choice of crystal, operating frequency, loop gain
and capacitor ratios. For details on timing, refer to the appropriate prod-
uct data sheet.
Pre-Divider Input
This unit divides the PLL input clock by 2 if enabled (using the INDIV
bit). The pre-divider input is part of the PLL loop, therefore, if a program
changes the PLL input clock (affecting the VCO frequency), the PLL
must be put in bypass mode before the change is made. This is described
in “Bypass Mode” on page 22-7.
To Next Page
Loading...
Need help?
General
