ADSP-214xx SHARC Processor Hardware Reference A-151
Registers Reference
SPORT Divisor Registers (DIVx)
These registers, shown in Figure A-85, allow programs to set the frame
sync divisor and clock divisor.
Serial Control Registers (SPCTLx)
The
SPCTLx registers are transmit and receive control registers for the cor-
responding serial ports (SPORT 0 through 7). These registers change
depending on operating mode. Figures and bit descriptions are provided
as follows.
• Serial mode – Figure A-86 and Table A-84 on page A-153.
•I
2
S and Left-Justified modes – Figure A-87 on page A-158 and
Table A-85 on page A-159.
• Packed and Multichannel mode – Figure A-88 on page A-162 and
Table A-86 on page A-163.
Figure A-85. DIVx Register (RW)
FSDIV
CLKDIV
Clock Divisor
Frame Sync Divisor
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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