Peripherals Routed Through the DAI
A-152 ADSP-214xx SHARC Processor Hardware Reference
Figure A-86. SPCTLx Register for Standard Serial Mode
DXS_A (3 1–30)
Data Buffer Channel A Status
LFS
Active Low Frame Sync
DERR_A
Channel A Error Status
SDEN_A
DMA Channel A Enable
DXS_B (28–27)
Data Buffer Channel B Status
DERR_B
Channel B Error Status
SPTRAN
SPORT Data Direction
SPEN_B
SPORT Enable B
BHD
Buffer Hang Disable
LAFS
Late Frame Sync
SCHEN_A
DMA Channel A
Chaining Enable
SDEN_B
DMA Channel B Enable
SCHEN_B
DMA Channel B Chaining
Enable
FS_BOTH
Frame Sync Both
SPEN_A
DIFS
Data Independent FS
IFS
Internally-Generated FS
FSR
Frame Sync Requirement
CKRE
Clock Edge for Data Frame
Sync Sampling
OPMODE
SPORT Operation Mode
DTYPE (2–1)
Data Type
ICLK
Internally Generated
SPORTx_CLK
SPORT Enable A
LSBF
Least Significant Bit Format
SLEN (8–4)
Serial word length–1
PACK
16/32 Packing
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
To Next Page
Loading...
