Interrupts
9-34 ADSP-214xx SHARC Processor Hardware Reference
DAI Interrupt Priorities
As described above, the DAI interrupt controller registers provide 32 inde-
pendently-configurable interrupts labeled DAI_INT31–0.
Just as the core has its own interrupt latch registers (IRPTL and LIRPTL),
the DAI has its own latch registers (
DAI_IMASK_L and DAI_IMASK_H). When
a DAI interrupt is configured to be high priority, it is latched in the
DAI_IMASK_H register. When any bit in the DAI_IMASK_H register is set
(= 1), bit 11 in the IRPTL register is also set and the core services that
interrupt with high priority. When a DAI interrupt is configured to be
low priority, it is latched in the DAI_IMASK_L register. Similarly, when any
bit in the DAI_IMASK_L register is set (= 1), bit 6 in the LIRPTL register is
also set and the core services that interrupt with low priority.
By default interrupts are mapped onto low priority interrupt.
DPI Interrupt Channels
The DPI can handle up to 12 interrupts as shown below.
• 1 TWI FIFO status
• 2 UART DMA channels
• 9 miscellaneous interrupts
DPI Interrupt Priorities
Just as the core has its own interrupt latch registers (IRPTL and LIRPTL),
the DPI has its own latch registers (
DPI_IMASK). When a DPI interrupt is
configured, it is latched in the
DPI_IMASK register. When any bit in the
DPI_IMASK register is set (= 1), bit 11 (DPII) in the IRPTL register is also set
and the core services that interrupt.
The DPI interrupt controller has no priority option.
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