Functional Description
2-28 ADSP-214xx SHARC Processor Hardware Reference
occurs because the I/O processor starts the first transfer before test-
ing the count value. The only way to disable a DMA channel is to
clear its DMA enable bit.
External Index Register Addressing
The external port DMA channels each contain additional parameter regis-
ters: the external index registers (
EIEPx), external modify registers (EMEPx),
and external count registers (ECEPx). The DMA controller generates 28-bit
external memory addresses over the IOD1 bus using the EIEPx register
during DMA transfers between internal memory and external memory.
Unlike previous SHARCs, all SPORT DMA channels can transfer data
from the SPORTs to the external memory space. This transfer uses the
28-bit IIxSPx register.
DMA Channel Status
There are two methods the processor uses to monitor the progress of
DMA operations; interrupts, which are the primary method, and status
polling. The same program can use either method for each DMA channel.
The following sections describe both methods in detail.
Programs can check the appropriate DMA status bits (for example the sta-
tus bits in the
SPMCTL register for the serial ports) to determine which
channels are performing a DMA or chained DMA. All DMA channels can
be active or inactive. If a channel is active, a DMA is in progress on that
channel. The I/O processor indicates the active status by setting the chan-
nel’s bit in the status register.
Note that there is 1 PCLK cycle latency between a change in DMA
channel status and the status update in the corresponding register.
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