ADSP-214xx SHARC Processor Hardware Reference A-73
Registers Reference
Period Registers (PWMPERIODx)
These 16-bit RW registers control the unsigned period of the four PWM
groups. This register is double buffered for double update mode. A change
in one half cycle of PWM switching period only takes effect in the next
half period.
Duty Cycle High Side Registers (PWMAx, PWMBx)
The 16-bit duty-cycle control registers (RW) directly control the A/B
(two’s-complement) duty cycles of the two pairs of PWM signals.
2 PWM_POL1AH Channel AH Polarity 1.
0 = Channel AH polarity 0
1 = Channel AH polarity 1 (default)
3 PWM_POL0AH Channel AH Polarity 0.
0 = Channel AHpolarity 0
1 = Channel AH polarity 1 (default)
4 PWM_POL1BL Channel BL Polarity 1.
0 = Channel AL polarity 0
1 = Channel AL polarity 1 (default)
5 PWM_POL0BL Channel BL Polarity 0.
0 = Channel AL polarity 0
1 = Channel AL polarity 1 (default)
6 PWM_POL1BH Channel BH Polarity 1.
0 = Channel BH polarity 0
1 = Channel BH polarity 1 (default)
7 PWM_POL0BH Channel BH Polarity 0.
0 = Channel BH polarity 0
1 = Channel BH polarity 1 (default)
15–8 Reserved
Table A-40. PWMPOLx Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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