ADSP-214xx SHARC Processor Hardware Reference 15-37
Serial Peripheral Interface Ports
5. Reconfigure the
SPICTLx registers to remove the clear condition on
the TXSPIx/RXSPIx registers.
6. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx registers using the SPIDEN bit (bit 0).
DMA Error Interrupts
The SPIUNF and SPIOVF bits of the SPIDMACx registers indicate transmission
errors during a DMA operation in slave mode. When one of the bits is set,
an SPI interrupt occurs. The following sequence details the steps to
respond to this interrupt.
With SPI disabled:
1. Disable the SPI port by writing 0x00 to the
SPICTLx registers.
2. Disable DMA and clear the DMA FIFO by FIFOFLSH bit in the
SPIDMACx register. This ensures that any data from a previous DMA
operation is cleared before configuring a new DMA operation.
3. Clear all errors by writing to the W1C-type bits in the SPISTATx
registers. This ensures that the error bits SPIOVF and SPIUNF (in the
SPIDMACx registers) are cleared when a new DMA is configured.
4. Reconfigure the
SPICTLx registers and enable the SPI using the
SPIEN bit.
5. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx registers.
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