Programming Model
15-36 ADSP-214xx SHARC Processor Hardware Reference
3. Disable DMA and clear the DMA FIFO by setting the
FIFOFLSH
bit is the SPIDMACx registers. This ensures that any data from a pre-
vious DMA operation is cleared because the SPICLK signal runs for
five more word transfers even after the DMA count falls to zero in
the receive DMA.
4. Clear all errors by writing to the SPISTATx registers. This ensures
that no interrupts occur due to errors from a previous DMA
operation.
5. Reconfigure the SPICTLx registers and enable the SPI.
6. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx registers using the SPIDEN bit (bit 0).
With enabled SPI:
1. Poll the SPIFE bit in the SPISTAT register. If this bit =1 the SPI can
be disabled.
2. Clear the RXSPIx/TXSPIx registers and the buffer status without dis-
abling the SPI by ORing 0xC0000 with the present value in the
SPICTLx registers. Use the RXFLSH (bit 19) and TXFLSH (bit 18) bits
in the SPICTLx registers to clear the RXSPIx/TXSPIx registers and
the buffer status.
3. Clear the DMA FIFO by the FIFOFLSH bit in the SPIDMACx register
without changing other bits. This ensures that any data from a pre-
vious DMA operation is cleared because
SPICLK runs for five more
word transfers even after the DMA count is zero in receive DMA.
The SPIDMACx register bits should not be changed because as this
will change the DMA direction and cause bad data to be transmit-
ted out, even with DMA disabled.
4. Clear all errors by writing to the W1C-type bits in the SPISTATx
registers. This ensures that no interrupts occur due to errors from a
previous DMA operation.
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