Programming Model
13-22 ADSP-214xx SHARC Processor Hardware Reference
desired mode in the transmitter control register. This setup can be accom-
plished in three steps.
1. Connect the transmitter’s four required input signals and one
biphase encoded output in the SRU. The four input signals are the
serial clock (
DIT_CLK_I), the serial frame sync (DIT_FS_I), the serial
data (DIT_DAT_I), and the high frequency clock (DIT_HFCLK_I) used
for the encoding. The only output of the transmitter is DIT_O.
2. If user bits are required, write 0x1 to the DITUSRUPD register for the
first block of transfer. Also route the DIT_BLK_START_O signal to the
DAI_INT_26 (DAI_IRPTLx register). This generates interrupts during
the last frame of the block (192), allowing changes of user bits for
the next block.
3. Initialize the DITCTL register to enable the data encoding.
4. Manually set the block start bit in the data stream once per block
(384 words). This is necessary if automatic generation of block
start information is not enabled in the DITCTL register, (DIT_AUTO =
0).
Programming the Receiver
Since the S/PDIF receiver data output is not available to the core, pro-
gramming the peripheral is as simple as connecting the SRU to the
on-chip (serial ports or input data port) or off-chip (DAI pins) serial
devices that provide the clock and data to be decoded, and selecting the
desired mode in the receiver control register. This setup can be accom-
plished in two steps.
1. Connect the input signal and three output signals in the SRU for.
The only input of the receiver is the biphase encoded stream,
DIR_I. The three required output signals are the serial clock
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