ADSP-214xx SHARC Processor Hardware Reference I-1
IINDEX
Numerics
128-channel TDM, 10-3
16-bit SDRAM address map, 3-28, 3-62
16-bit word, 3-16, 10-45
16-bit word, boot packing, 23-19
32/40-bit floating-point mode, IIR
accelerator, 6-61
32-bit word, 3-89, 3-117, 5-4, 10-40,
10-41, 10-43, 11-6, 11-7, 11-10,
11-12, 11-19
32-bit word, boot packing, 23-18
32- to 40-bit packing, IIR, 6-62
48-bit word, 3-90
48-bit word, boot packing, 23-15
8-bit boot (SPI), 23-17
8-bit word, 3-14, A-49
8-bit word, boot packing, 23-20
A
AAC compressed format, 13-17
AC-3 format, 13-17
accuracy (PWM), 7-23
active low frame sync select for frame sync
(INVFSx) bit, 14-13
active state multichannel receive frame sync
select (LMFS) bit, 10-20
AD1855 stereo DAC, use with SPI, 15-10
address
AMI, 3-84
AMI address map, 3-14
core to external memory, 3-27
address (continued)
decoding address bank, 3-27, 3-62
destination, 2-22
instruction execution from external
memory, 3-89
internal/external index, 2-36
logical vs. physical, 3-90
map, 16-bit SDRAM, 3-28, 3-62
predictive, 3-14
SDRAM, 3-22, 3-24
SDRAM read, 3-40
addressing
7-bit in TWI, 21-2
AMI, external, 3-14, 3-15
byte in SDRAM, 3-68
general call in TWI, 21-14
IOP, 2-25
mixing instructions and data, 3-93
alarm clock, RTC, 18-7
AMI
See also external port, SDRAM, shared
memory
ADDR23-0 bits, 3-14
address map, 3-14
control (AMICTLx) register, A-21 to
A-23, A-47 to A-50
DMA, 3-10
external memory addressing, 3-14, 3-15
memory bank support, 3-14
reading external memory, 3-84
read/write throughput, 3-117
To Next Page
Loading...
