ADSP-2147x, ADSP-2148x External Port Registers
A-50 ADSP-214xx SHARC Processor Hardware Reference
16–14 IC Bus Idle Cycle. Default Idle cycles are inserted whenever read to
write in a bank or read to read between two external banks or a read
to the SDC happened.
000 = 0 cycles, 001 = 1 cycle
010 = 2 cycles, 011 = 3 cycles
100 = 4 cycles, 101 = 5 cycles
110 = 6 cycles, 111 = 7 cycles
A bus idle cycle is an inactive bus cycle that the processor automati-
cally generates to avoid data bus driver conflicts. Such a conflict can
occur when a device with a long output disable time continues to
drive after
RD is deasserted, while another device begins driving on
the following cycle. Idle cycles are also required to provide time for
a slave in one bank to three-state its ACK driver, before the slave in
the next bank enables its ACK driver.
17 (WO) AMIFLSH AMI Buffer Flush. Flushes both AMIRX and AMITX buffers.
0 = Buffer holds the data
1 = Flush the buffer
20–18 RHC Read Hold Cycle. Controls the delay between two reads.
000 = Disable read hold cycle
001 = Hold address for one cycle
010 = Hold address for two cycles
A read hold cycle is the delay between two reads at the end of a read
access. Programs may disable the read hold cycle, or hold the
address for one or more external port clock cycles.
21 PREDIS Disable Predictive Reads. Default is predictive reads are enabled.
Note this bit is global, if set it does apply to all external banks.
31–22 Reserved
Table A-26. AMICTLx Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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