ADSP-214xx SHARC Processor Hardware Reference 14-21
Precision Clock Generator
Programming should occur in the following order.
1. Program the
PCG_SYNC and the PCG_CTLA0–1, PCG_CTLB0–1 registers
appropriately.
2. Enable clock or frame sync, or both.
Since the rising edge of the external clock is used to synchronize with the
frame sync, the frame sync output is not generated until a rising edge of
the external clock is sensed.
Debug Features
Care should be taken in cases where any input to the phase unit is modi-
fied. Any individual change of the CLKDIV or FSDIV dividers may cause a
failure in PCG sync operation between the serial clock and the frame sync.
Only the programming model ensures a correct setup for phase settings.
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