ADSP-214xx SHARC Processor Hardware Reference 17-5
Shift Register – ADSP-2147x
Functional Description
The Shift Register module consists of an 18-stage serial shift register,
18-bit latch, and three-state output buffers. Three-state buffers are imple-
mented in I/O buffers. The shift register and latch have separate clocks.
Data is shifted on the positive-going transitions of the SR_SCLK_I input.
The data in each flip-flop is transferred to the respective latch on a posi-
tive-going transition of the SR_LAT_I input. The shift register has a serial
data input (SR_SDI_I) and a serial data output (SR_SDO_O) for cascading.
A common active low asynchronous reset (SR_CLR_I) is provided for
18-bit shift register and for 18-bit latch. As shown in the Figure 17-1, the
latch has 18 parallel outputs to drive three-state output buffers. Data in
the latch appears at the output whenever the output enable input
(SR_LDOE_I) is high. The SR_CLR_I signal is derived from an external pin
(SR_CLR), and a software programmable reset (SR_CTL1). If either of these
two signals goes low, then SR_CLR_I goes low. The serial data output
(SR_SDO_O) can be selected from any one of the 18-bit register’s outputs.
Selection of the source is provided through software using the SR_CTL reg-
ister. A common active low asynchronous reset (SR_CLR_I) is provided for
the shift register and for the latch.
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