Analog Devices SHARC ADSP-214 Series - V; W

Index
I-32 ADSP-214xx SHARC Processor Hardware Reference
UART (continued)
sampling point, 20-11
standard, 20-1
timers, 20-6
UART bits
9-bit RX enable (RX9), A-250
9-bit TX enable (TX9), A-250
address detect enable (UARTAEN),
A-250
DMA TX/RX control, A-251
DMA TX/RX status, A-252
enable receive buffer full interrupt
(UARTRBFIE), A-246
enable transmit buffer empty interrupt
(UARTTBEIE), A-246
interrupt enable, A-247
pack data, 20-8
packing enable (PACK), A-250
pin status (UARTPSTx), A-251
program controlled interrupt bit (PCI),
20-22
synch data packing in RX
(UARTPKSYN), A-250
THR register empty (UARTTHRE),
A-245
UARTNOINT (pending interrupt),
A-248
UARTSTAT (interrupt), A-248
UART registers
divisor latch register
(UARTxDLL), 20-4, A-249
divisor latch (UARTxDLH), 20-4,
A-249
interrupt enable register (UARTxIER),
A-246
interrupt identification register
(UARTxIIR), A-247
line control register (UARTxLCR),
A-243
line status register (UARTxLSR), A-245
receive buffer register (UARTxRBR),
20-11
transmit holding (UARTxTHR), 20-10
transmit shift register (UART_TSR),
20-10
UARTxDLH (divisor latch register),
20-4, A-249
UARTxDLL (divisor latch register),
20-4, A-249
UARTxIER (interrupt enable register),
A-246
UARTxIIR (interrupt identification
register), A-247
UARTxLCR (line control register),
A-243
UARTxLSR (line status register), A-245
UARTxRBR (receive buffer register),
20-11
UARTxTHR (transmit holding register),
20-10
UARTxTSR (transmit shift register),
20-10
V
VCO
bypass clock, 22-7
clock, 22-5
examples, clock management, 22-15
output clock, 22-5
W
wait states, enabling (WS bit), A-22, A-49
warnings and cautions
DMA transfers, 2-28
I/O processor, 2-28
SPORTs, 10-42
watchdog function, timer, 16-19
watchdog timer
clocking, 19-4
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