Peripherals Routed Through the DPI
A-248 ADSP-214xx SHARC Processor Hardware Reference
This can be established by globally assigning all UART interrupts to the
same interrupt priority. For more information, see Appendix B, Peripheral
Interrupt Control.
There is also a shadow register,
UART0IIRSH. This register allows programs
to read the contents of the corresponding main register without affecting
the status of the UART.
Figure A-139. UART0IIRSH Register
Table A-130. UART0IIRSH Register Bit Descriptions (RO)
Bit Name Description
0 UARTNOINT Pending Interrupt. When UARTNOINT bit cleared it signals that
an interrupt is pending.
0 = Interrupt pending
1 = No interrupt pending (default)
3–1
(ROC
1
)
1 These bits are read-only in the UARTxLRSH (shadow) register.
UARTISTAT In the Order of Interrupt Priority, Highest First.
011 = Receive line status. Read UART_LSR to clear interrupt
request.
100 = Address detect. Read RBR to clear interrupt request.
010 = Receive data ready. Read UART RBR to clear interrupt
request.
001 = UART_THR empty. Write UART_THR or read UART_IIR
to clear interrupt request, when priority = 4.
000 = UART THR & TSR empty (TEMT = transmit complete).
Write UART_THR or read UART_IIR to clear interrupt request,
when priority = 5. In the case where both interrupts are signalling,
the UARTxIIR register reads 0x06. When a UART interrupt is
pending, the interrupt service routine (ISR) needs to clear the
interrupt latch explicitly.
UARTISTAT (3–1)
In the order of interrupt priority, highest first
Pending Interrupt
UARTNOINT
09 837564 2114 12 11 101315
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