Index
I-4 ADSP-214xx SHARC Processor Hardware Reference
clock A source (CLKASOURCE) bit,
A-193
clock input (CLKIN) pin, 17-5
clocks
RTC, 18-3
clocks and system clocking, 22-2
clock and frame sync frequencies (DIVx)
registers, 10-8
clock distribution, 23-33
clock polarity (CLKPL) bit, A-234
clock rising edge select (CKRE) bit,
A-155, A-164
core clock, 22-6
disabling the clock, 22-6
hardware control, 22-4
internal clock select (ICLK) bit, A-154,
A-159, A-163
managing for power savings, 22-12
output divider, 22-4
peripheral clock, 22-6
precision clock generator registers, 14-21
SDRAM controller, 3-6
selecting clock ratios, 22-4
software control, 22-4
source select (MSTR) bit, A-154, A-159,
A-163
SPI clock phase select (CPHASE) bit,
A-234
SPORTs, 10-8
VCO encodings, 22-5
coefficient memory, FIR, 6-33
commands
auto-refresh, 3-24
bank activate, 3-21
load mode register, 3-21
NOP, 3-24
precharge, 3-21, 3-22
read/write, 3-22
self-refresh, 3-44, 3-79
compand data in place, 10-3
companding (compressing/expanding),
10-3
compute block, FFT, 6-5
conditioning input signals, 23-33
configuring frame sync signals, 10-11
connecting peripherals through DAI, 9-16
connections
group A, clock signals, 9-24
group A, DPI, input routing signals,
A-218
group B, DPI, pin assignment signals,
A-223
group C, DPI, pin enable signals, A-227
continuous mode,
See SPORTs
, framed
and unframed data
controller, SDRAM, 3-17
conventions, -lxx
core access read optimization, 3-42, 3-78
core address mapping, 3-27
core transmit/receive operations, 15-20
count (CSPx) DMA registers, 2-6
count (CSPx) registers, 2-27
counters
RTC, 18-4
count (IDP_DMA_Cx) registers, 11-20,
11-21
crosstalk, reducing, 23-37
CSPx (peripheral DMA counter) registers,
2-6, 2-27
customer support, -lxvi
D
DAI
clock routing control registers (group A),
9-24
configuration macro, 9-43
connecting peripherals with, 9-16
control registers, clock routing control
registers (Group A), A-118
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