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DDR2 DRAM Controller (ADSP-2146x)

3-78 ADSP-214xx SHARC Processor Hardware Reference

Listing 3-4. Maximum Throughput Using Sequential Reads

ustat1=dm(DDR2CTL0);

bit set ustat1 DDR2OPT|DDR2MODIFY1;

dm(DDR2CTL0)=ustat1;

nop;

I0 = DDR2_addr;

M0 = 1;

Lcntr = 1024, do(PC,1) until lce;

R0 = R0 + R1, R0 = dm (I0, M0);

The example shows read optimization can be used efficiently using core

accesses. All reads are on the same page and it takes 1044 cycles to perform

1024 reads.

Without read optimization, 1024 reads use 5125 processor cycles if all of

the reads are on the same page, non-sequential reads takes 9220 cycles.

With read optimization (Listing 3-5), 1024 reads take 10262 cycles, due

to the breaking of sequential reads.

Listing 3-5. Interrupted Reads With Read Optimization

ustat1=dm(DDR2CTL0);

bit set ustat1 DDR2OPT|DDR2MODIFY2;

dm(DDR2CTL0)=ustat1;

nop;

I0 = DDR2_addr;

M0 = 2;

Lcntr = 1024, do(PC,2) until lce;

R0 = R0 + R1, R0 = dm (I0, M0);

NOP;

Note the above mentioned cycles may vary based on different latency and

timing parameters programmed.

DMA Access

Listing 3-6 shows an example of external port DMA using read

optimization.

Analog Devices SHARC ADSP-214 Series User Manual

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