ADSP-214xx SHARC Processor Hardware Reference 13-21
Sony/Philips Digital Interface
Debug Features
The following feature supports S/PDIF debugging.
Loop Back Routing
The S/PDIF supports an internal loopback mode by using the SRU. For
more information, see “Loop Back Routing” on page 9-40.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Programming Model
The following sections provide information on programming the trans-
mitter and receiver.
Programming the Transmitter
Since the S/PDIF transmitter data input is not available to the core, pro-
gramming the transmitter is as simple as: 1) connecting the SRU to the
on-chip (serial ports or input data port) or off-chip (DAI pins) serial
devices that provide the clock and data to be encoded, and 2) selecting the
To Next Page
Loading...
Need help?
General
