ADSP-214xx SHARC Processor Hardware Reference 7-13
Pulse Width Modulation
therefore be programmed in increments of 2
× PCLK (or 10 ns for a 200
MHz peripheral clock). The PWMDTx registers are 10-bit registers, and the
maximum value they can contain is 0x3FF (= 1023) which corresponds to
a maximum programmed dead time of:
This equates to an PCLK rate of 200 MHz. Note that dead time can be pro-
grammed to zero by writing 0 to the PWMDTx registers (see “Pulse Width
Modulation Registers” on page A-67).
Output Control Unit
The PWMSEG register contains four bits (0 to 3) that can be used to individ-
ually enable or disable each of the 4 PWM outputs.
Output Enable
If the associated bit of the PWMSEG register is set (=1), then the correspond-
ing PWM output is disabled, regardless of the value of the corresponding
duty cycle register. This PWM output signal remains disabled as long as
the corresponding enable/disable bit of the PWMSEGx register is set. In sin-
gle update mode, changes to this register only become effective at the start
of each PWM cycle. In double update mode, the
PWMSEG register can also
be updated at the mid-point of the PWM cycle.
After reset, all four enable bits of the PWMSEG register are cleared so
that all PWM outputs are enabled by default.
Output Polarity
The polarity of the generated PWM signals is programmed using the
PWMPOLARITY3–0 registers, so that either active high or active low PWM
patterns can be produced. The polarity values can be changed on the fly if
T
dmax,
1023 2× t
PCLK
× 1023 2× 10 10
9–
×× 10.2μs===
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