ADSP-214xx SHARC Processor Hardware Reference 16-19
Peripheral Timers
Watchdog Functionality
Any of the timers can be used to implement a watchdog functionality that
can be controlled by either an internal or an external clock source.
For a program to service the watchdog, the program must reset the timer
value by disabling and then re-enabling the timer. Servicing the watchdog
periodically prevents the count register from reaching the period value and
prevents the timer interrupt from being generated. When the timer
reaches the period value and generates the interrupt, reset the processor
within the corresponding watchdog’s ISR.
Debug Features
The following section provides information on debugging features avail-
able with the timer.
Loopback Routing
An emulation halt will not stop the timer period counter.
Loopback Routing
The timer support an internal loopback mode by using the SRU. For
more information, see “Loop Back Routing” on page 9-40.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
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