ADSP-214xx SHARC Processor Hardware Reference 10-47
Serial Ports
DMA Chaining
Each channel also has a DMA chaining enable bit (SCHEN_A and SCHEN_B)
in its SPCTLx control register.
Each SPORT DMA channel also has a chain pointer register (CPSPxy).
The
CPSPxy register functions are used in chained DMA operations.
In chained DMA operations, the processor’s DMA controller automati-
cally sets up another DMA transfer when the contents of the current
buffer have been transmitted (or received). The chain pointer register
(
CPSPxy) functions as a pointer to the next set of buffer parameters stored
in external or internal memory. The DMA controller automatically down-
loads these buffer parameters to set up the next DMA sequence. For more
information on SPORT DMA chaining, see “DMA Chaining” on
page 2-32.
DMA chaining occurs independently for the transmit and receive channels
of each serial port. Each SPORT DMA channel has a chaining enable bit
(SCHEN_A or SCHEN_B) that when set (= 1), enables DMA chaining and
when cleared (= 0), disables DMA chaining. Writing all zeros to the
address field of the chain pointer register (CPSPxy) also disables chaining.
The chain pointer register should be cleared first before chaining is
enabled.
The I/O processor responds by auto-initializing the first DMA parameter
registers with the values from the first TCB, and then starts the first data
transfer.
Although the word lengths can be 3 to 32 bits, transmitting or
receiving words smaller than 7 bits at the full clock rate of the serial
port may cause incorrect operation when DMA chaining is
enabled. Chaining locks the processor’s internal I/O bus for several
cycles while the new transfer control block (TCB) parameters are
being loaded. Receive data may be lost (for example, overwritten)
during this period.
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