DDR2 DRAM Controller (ADSP-2146x)
3-74 ADSP-214xx SHARC Processor Hardware Reference
0x200A00 logical start address int bankF
0x200BFF logical end address int bankF
0x200C00 logical start address int bankG
0x200DFF logical end address int bankG
0x200E00 logical start address int bankH
0x201000 logical end address int bankH
Bank Interleaving (DDR2ADDRMODE bit = 1):
0x200000 logical start address int bankA
0x2001FF logical end address int bankA
0x600000 logical start address int bankB
0x6001FF logical end address int bankB
0xA00000 logical start address int bankC
0xA001FF logical end address int bankC
0xE00000 logical start address int bankD
0xE001FF logical end address int bankD
0x1200000 logical start address int bankE
0x12001FF logical end address int bankE
0x1600000 logical start address int bankF
0x16001FF logical end address int bankF
0x1A00000 logical start address int bankG
0x1A001FF logical end address int bankG
0x1E00000 logical start address int bankH
0x1E001FF logical end address int bankH
Fixed Timing Parameters
The timing specifications below are fixed by the controller.
•t
MRD
(mode register delay). Required delay time to complete the
mode register write. This parameter is fixed to 2 cycles.
•t
RC
(row access cycle). Required delay time to open and close a sin-
gle row. This parameter is fixed to t
RC
=t
RAS
+ t
RP
cycles.
•t
CCD
(column to column delay). Required delay between two col-
umn accesses (read/write). This parameter is fixed to 2 cycles.
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