Operating Modes
15-12 ADSP-214xx SHARC Processor Hardware Reference
SPIDS pins to the DPI pins of the master SHARC. Since these flags are
NOT open drain, slave select pins cannot be shorted together in multi
master environment. To control slave selects, an external glue logic is
required in a multi-master environment.
Another feature is implemented to troubleshoot the bus mastership proto-
col. If a recent SHARC bus master receives an invalidly asserted SPIDS
signal, it triggers an error handling scenario using the MME bit (SPIMME bit
for DMA) and ISSEN bit to reconfigure the SPI to slave mode, and jump
into an ISR. This ensures that any potential driver conflict is solved. For
more information, see “Control Registers (SPICTL, SPICTLB)” on
page A-232.
Operating Modes
This sections describes the different mechanisms used for master or slave
select operation modes.
Figure 15-4. Multi Master System
SPIFLGxy
SPI #1
SPIFLGxy
SPI #2
SPIFLGxySPI_DS_I
SPI #3
SPICLK
SPI_MOSI_PBEN_O (open drain)
SPI_MISO_PBEN_O (open drain)
BUS ARBITRATION LOGIC
SPI_DS_I SPI_DS_I
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