Peripheral Registers
A-96 ADSP-214xx SHARC Processor Hardware Reference
System Status Register (MLB_SSCR)
This register, shown in Figure A-46 and described in Table A-58, allows
system software to monitor and control the status of the MLB network.
The register is updated once per frame by hardware during the MLB sys-
tem channel. The bits of this register are not valid until the ADSP-214xx
is locked to the MLB interface (except for the bits associated with MLB
lock and unlock, SDMU and SDML). System software must service events
before the start of the next MLB frame to prevent the current frame status
from being lost.
29–28 MCS MLB Clock Select.
00 = 256Fs – supports 8 quadlets per frame
01 = 512Fs – supports 16 quadlets per frame
10 = 1024Fs – supports 32 quadlets per frame
11 = reserved
30 LBM Loopback Mode Enable.
0 = Loopback disabled
1 = Loopback enabled
31 MDE MLB Enable.
0 = MLB disabled
1 = MLB enabled
Figure A-46. MLB_SSCR Register
Table A-57. MLB_DCCR Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
SDNL
SDNU
SDCS
SDML
SDR
System Detects Reset Command
System Detects MLB Unlock
SSRE
System Service Request Enable
SDSC
System Detects Subcommand
System Detects MLB Lock
SDMU
09 837564 2114 12 11 101315
System Detects Network Lock
System Detects Network Unlock
System Detects Channel Scan
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