Index
I-2 ADSP-214xx SHARC Processor Hardware Reference
AMI (continued)
status (AMISTAT) register, A-23, A-24,
A-51
timing, 3-7
AMI bits
ACK pin enable (ACKEN), A-22, A-49
buffer flush (FLSH), A-23, A-50
bus hold cycle (HC), A-22, A-49
bus idle cycle (HC), A-23, A-50
external bus data width (BW), A-22
most significant word first (MSWF),
A-22, A-49
packing disable (PKDIS), A-22, A-49
predictive read disable (NO_OPT),
A-23, A-50
read hold cycle (RHC), A-23, A-50
wait state enable (WS), A-22, A-49
AMIEN, A-22, A-48
arbitration, channel, 2-36
arbitration, fixed/floating, 2-43
architecture
TWI controller, 21-7
array, hold TCB, 2-35
asynchronous memory interface. See AMI
asynchronous serial communications
(UART), 20-7
audience, intended, -lxi
audio
biphase encoded in S/PDIF, 13-3
data formats, IDP, 11-16
formats, IDP, 11-6
formats, S/PDIF, 13-7, 13-15
non-linear data, S/PDIF, 13-16
restriction with SPORTs, 10-10
transmission standards, SPORTs, C-3
audio formats, C-1 to C-9
audio modes, C-2 to C-9
autobaud detection, 20-6
automotive products, 1-2
B
bank
DDR2 address mapping, 3-65, 3-66
SDRAM address mapping, 3-25 to 3-30
base registers, 2-8
baud rate, 23-13
setting, 15-30
UART, 20-5, 20-10, 20-11
BHD (buffer hang disable) bit, 10-54
bidirectional connections through the
signal routing unit, 9-14
bidirectional functions (transmit, receive),
10-3
biphase
encoded audio stream, 13-4, 13-14
routing data, 13-5
bits See peripheral specific bits, bits by
name or acronym
block diagram
FFT accelerator, 6-6
IDP, 11-7
IDP channel 0, 11-9
I/O processor, 2-30
PWM, 7-2
S/PDIF transmitter, 13-8
SPI, 15-9
SPORTs, 10-13
SRC, 12-6
TWI controller, 21-7
block diagrams
RTC, 18-8
boolean operator
OR, 11-32
booting, 23-7 to 23-28
bootstrap loading, 23-7
DMA use in, 2-23
link port, 23-21
SPI master mode, 23-12
SPI packing, 23-17
SPI slave, 23-15
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