Index
I-20 ADSP-214xx SHARC Processor Hardware Reference
power management control register
(PMCTL), 22-4, A-8, A-13
power management examples, 22-12
power management register, A-10, A-16
power savings, 22-6, 22-12
power savings tips, 22-13
power supply, monitor and reset generator,
23-42
power-up, SDRAM (SDPM) bit, A-53
power-up, See system design
power-up reset circuit, 23-42
preambles, S/PDIF, C-16
precision clock generators. See PCG
predictive address vs. real address, 3-14
predictive reads, disable bit (NO_OPT),
A-23, A-50
printed circuit board design, 23-37
priority, interrupt, 2-48
processor, host, 23-7
processor core
access to link buffers, 4-15
processor core, overview, 1-2
processor reset, 23-3
product details, 1-2
program control interrupt (PCI) bit, 2-13
program controlled interrupt bit (PCI),
2-12, 2-13, 6-18, 10-48, 15-13,
20-22, A-167
programmable interrupt registers (PICRx),
B-4
programmable interrupts, listed, 2-48, B-6
programming example, 6-71
programming model, 6-68
TWI controller, 21-19
pulse, clock, in serial ports, 10-11
pulse, frame sync delay in serial ports,
10-33
pulse, frame sync formula, 10-9
pulse width count and capture
(WDTH_CAP) mode, 16-12
pulse width modulation (PWMOUT)
mode, 16-8
PWM
16-bit read/write duty cycle registers, 7-7
accuracy in, 7-23
block diagram, 7-2
center-aligned paired PWM
double-update mode, 7-
10
channel duty control (PWMA, PWMB)
registers, A-73
crossover mode, 7-14
equations, 7-8 to 7-12
global control (PWMGCTL) register,
A-67
global status (PWMGSTAT) register,
A-69
switching frequency equation, 7-6
PWM bits
crossover (PWM_AXOV,
PWM_BXOV), 7-14
PWMGCTL (pulse width modulation
global control) register, A-67
PWMGSTAT (pulse width modulation
global status) register, A-69
PWMOUT (pulse width modulation)
mode, 16-8
R
real time clock
see RTC
real-time clock. See RTC
receive busy (overflow error) SPI DMA
status (SPIOVF) bit, A-238
receive data, serial port (RXSPx) registers,
2-10
receive data (RXSPI) buffer, 15-8
receive overflow error (SPIOVF) bit,
15-26, 15-37, 15-38
receive shift (RXSR) register, 15-8
refresh rate control (SDRRC) register, A-58
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