ADSP-214xx SHARC Processor Hardware Reference I-19
Index
peripheral timers (continued)
invalid conditions, 16-9
modes, 16-5
period, configuring, 16-4
period equation, 16-11
pulse width count and capture
(WDTH_CAP) mode, 16-12
pulse width modulation (PWMOUT)
mode, 16-8
rectangular signals, 16-10
RTI instruction, 16-18
single pulse generation, 16-11
TIMERx pin, 16-6
watchdog, 16-19
word count (TMxCNT) registers, 16-6
peripheral timers registers, 16-4
high word period (TMxPRD) registers,
16-6
high word pulse width (TMxW)
registers, 16-6
period (TMxPRD) registers, 16-4
pulse width (TMxW) registers, 16-5
timer control (TMxCTL), 16-6
timer count (TMxCNT), 16-4, 16-6
timer global status and control
(TMSTAT), 16-4
timer width (TMxW), 16-5
timer word period (TMxPRD), 16-4
word count (TMxCNT) registers, 16-4
phase shift of frame sync, 14-16
physical vs. logical address, 3-90
PICR (programmable interrupt priority)
registers, B-4
PICR register, 2-48, B-6
pin
buffer example, 9-7
ping-pong DMA, 2-23, 2-24
ping-pong DMA, IDP, 11-21
pins
ACK, enabling, A-22, A-49
descriptions, 22-18, 23-2
external memory, 3-48
FLAGx, 10-12
pin states during SDRAM commands,
3-25
RESET
, 23-34
timer (through SRU), 16-5
plane, ground, 23-37
PLLBP (PLL bypass bit), 22-7, A-11, A-16
PLLBP (PLL bypass mode) bit, 22-7, 22-15
PLLDx (PLL divider) bits, A-8, A-10,
A-11, A-13, A-16
PLLM (PLL multiplier) bit, A-8, A-10,
A-13, A-16
PLL start-up, 22-9
PMCTL (power management control)
register, 22-4, A-7, A-8, A-10, A-12,
A-13, A-16
polarity
IDP left-right encoding, 11-18
PWM double-update mode, 7-10
PWM single update mode, 7-9
SPDIF connections, C-14
SPI clock, 15-14, 15-29
power management
additional information, 22-13
bypass mode (PLL) example, 22-18
clocking system, 22-2
clock system, 22-2
disabling peripherals, 22-10 to 22-12
IDLE instruction use in, 22-13
phase-locked loop (PLL), 22-2
PLL, 22-9
post divider example, 22-14
registers (PMCTLx), 22-1
VCO programming example, 22-15
power management control (PMCTL)
register, A-7, A-12
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