ADSP-214xx SHARC Processor Hardware Reference B-1
B PERIPHERAL INTERRUPT
CONTROL
This appendix provides information about controlling interrupts as well as
a complete listing of the registers that are used to configure and control
programmable interrupts. For information on the IRPTL, LIRPTL, and
IMASK registers, see the SHARC Processor Programming Reference.
Interrupt Latency
The following
• For peripherals such as the timer or PWM which generate inter-
rupts, a write into the peripheral’s status register to clear the
interrupt causes a certain amount of latency (due to the existence of
register write effect latency).
• Interrupt-driven data transfers (core or DMA) from any peripheral
that generates interrupts and which uses an ISR routine, a write
into a peripheral data buffer (to clear the interrupt) or a control
register causes a certain amount of latency (due to the existence of
register write effect latency and buffer clock domains).
In both cases, if for example the program comes out of the interrupt ser-
vice routine (RTI instruction) during that period of latency (maximum of
10
CCLK cycles), the interrupt is generated again. To avoid interrupt regen-
eration, use one of the following solutions.
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