Operating Modes
14-12 ADSP-214xx SHARC Processor Hardware Reference
Normal Mode
When the frame sync divisor is set to any value other than zero or one, the
PCGs operates in normal mode. In normal mode, the frequency of the
frame sync output is determined by the divisor where:
The high period of the frame sync output is controlled by the value of the
pulse width control. The value of the pulse width control should be less
than the value of the divisor.
The phase of the frame sync output is determined by the value of the
phase control. If the phase is zero, then the positive edges of the clock and
frame sync coincide when:
• the clock and frame sync dividers are enabled at the same time
using an atomic instruction
• the divisors of the clock and frame sync are the same
• the source for the clock and frame sync is the same
The number of input clock cycles that have already elapsed before the
frame sync is enabled is equal to the difference between the divisor and the
phase values. If the phase is a small fraction of the divisor, then the frame
sync appears to lead the clock. If the phase is only slightly less than the
frame sync divisor, then the frame sync appears to lag the clock. The
frame sync phase should not be greater than the divisor.
Input Frequency
Divisor
Frequency of Frame Sync Output =
(
)
To Next Page
Loading...
Need help?
General
